Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme