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Multicore architecture to reduce power consumption while distributing heat uniformly
Pandi, Koteswara Rao
Pandi, Koteswara Rao
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Pandi_2024.pdf
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2024-04-26
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Pandi, K.R. 2024. Multicore architecture to reduce power consumption while distributing heat uniformly. -- In Proceedings: 20th Annual Symposium on Graduate Research and Scholarly Projects. Wichita, KS: Wichita State University
Abstract
INTRODUCTION: Uniform and Non-Uniform Subnet Architectures are lacking in resources utilization on chip. Resulting in spotty heat distribution, frequent reuse of specific cores and ultimately reducing performance, life span of silicon die. To overcome these challenges a stringent Wireless Network on Chip (WNoC) with a combination of router and core computational devices is the promising solution. Three architectures are studied to prove the concept. PURPOSE: The purpose of our study was to prove that proposed algorithm and system architecture improves performance while reducing power consumption and disperses temperature everywhere. METHODS: Algorithm with two steps of sorting process and a flag parameter is included to ensure that every computing system is exploited. To reduce power consumption involvement of intermediate nodes are abated by involving routers which can execute the instructions along with maintaining the directory. Three architectures (7x7) are studied by varying number of routers and cores. RESULTS: Considered 92 Jobs of industrial standard with arrival time, priority, tasks, and execution time are administered by the set of rules over the three different structures. Contemplated hop count, communication latency, and power consumption as the performance parameter and achieved 45.83%, 19.28%, and 37.16% respectively. In total 1058 units of time are requested by the application jobs, which were distributed between 15 to 24 units to every device using newly build process. When compared In-order execution the range is from 9 to 30 units. CONCLUSION: Improvement in performance is accomplished by increasing the number of routers. Limitation of our study included: (1) Every computational device will be accompanied with L1 independent cache and L2 shared cache to condense main memory requests. (2) Each requested job will have 3-5 tasks which will be executed parallelly by a single core or router. This concept can be extended by simulating CPU-GPU combinations.
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Presented to the 20th Annual Symposium on Graduate Research and Scholarly Projects (GRASP) held at the Rhatigan Student Center, Wichita State University, April 26, 2024.
Research completed in the Department of Electrical and Computer Engineering, College of Engineering.
Research completed in the Department of Electrical and Computer Engineering, College of Engineering.
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Wichita State University
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GRASP
v. 20
v. 20