An effective locking-free caching technique for power-aware multicore computing systems

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Issue Date
2014-05-23
Authors
Asaduzzaman, Abu
Allen, Mark P.
Jareen, Tania
Advisor
Citation

Asaduzzaman, A.; Allen, M.P.; Jareen, T., "An effective locking-free caching technique for power-aware multicore computing systems," Informatics, Electronics & Vision (ICIEV), 2014 International Conference on , vol., no., pp.1,6, 23-24

Abstract

In multicore/manycore systems, multiple caches increase the total power consumption and intensify latency because it is nearly impossible to hide last-level latency. Studies suggest that there are opportunities to increase the performance to power ratio by locking selected memory blocks inside the caches during runtime. However, the cache locking technique reduces the effective cache size and may introduce additional configuration difficulties, especially for multicore architectures. Furthermore, there may be other restrictions (example: PowerPC 750GX processor does not allow cache locking at level-1). In this paper, we propose a Smart Victim Cache (SVC) assisted caching technique that eliminates traditional cache locking without compromising the performance to power ratio. In addition to functioning as a normal victim cache, the proposed SVC holds memory blocks that may cause higher cache misses and supports stream buffering to increase cache hits. We model a Quad-Core System that has Private First Level Caches (PFLCs), a Shared Last Level Cache (SLLC), and a shared SVC located between the PFLCs and SLLC. We run simulation programs using a diverse group of applications including MPEG-4 and H.264/AVC. Experimental results suggest that the proposed SVC added multicore cache memory subsystem helps decrease the total power consumption and average latency up to 21% and 17%, respectively, when compared with that of SLLC cache locking mechanism without SVC.

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