Computer applications: A novel architecture to improve the performance of audio visual applications

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Issue Date
2022-12
Authors
Asaduzzaman, Abu
Chidella, Kishore K.
Sibai, Fadi N.
Advisor
Citation

Asaduzzaman, A., Chidella, K.K., Sibai, F.N. (2022). Computer applications: A novel architecture to improve the performance of audio visual applications. Journal of Management & Engineering Integration, 15(2), 110-123.

Abstract

To attain the best audio-visual experience, the underlying computing platform should provide high performance in real time. The forthcoming computer systems consist of multicore processors to achieve a high performance-to-power ratio. The algorithms in visual computing are becoming highly complex to meet the requirements. According to the new design paradigm, a simultaneous exploration of multicore architecture and complicated algorithms is beneficial to achieve the design goals for visual systems. However, caches in multicore architecture multiply the timing unpredictability and that creates a serious challenge in running real-time audio/visual applications in multicore systems. In this work, we introduce a novel multicore architecture with miss tables inside level-1 caches to improve performance and decrease power consumption. Miss table holds block address information regarding the application being processed that causes cache misses. Miss table information is used for efficient selection of the blocks to be locked or victim blocks to be replaced. This approach improves predictability by locking important blocks inside the cache during the execution time. At the same time, this approach decreases average delay per task and total power consumption by reducing cache misses when the right cache blocks are locked and/or replaced. We simulate an 8-core architecture that has 2 levels of caches using the Moving Picture Experts Group (MPEG)-4 decoding and Fast Fourier Transform (FFT) workloads. Simulation results show that a reduction of 42% in mean delay per task and a reduction of 40% in total power consumption are achieved by locking 20% of the total level-1 instruction (I1) cache size.

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Published in SOAR: Shocker Open Access Repository by Wichita State University Libraries Technical Services, November 2022.
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