Designing multi-core architecture using folded torus concept to minimize the number of switches

dc.contributor.advisorAsaduzzaman, Abu
dc.contributor.authorChaturvedula, Sri Ramya
dc.date.accessioned2012-06-19T17:19:04Z
dc.date.available2012-06-19T17:19:04Z
dc.date.copyright2011en
dc.date.issued2011-12
dc.descriptionThesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and Computer Science.en_US
dc.description.abstractA multi-core system provides improved performance/power ratio than a single-core one. However, multi-core architecture suffers from thermal constraint and data inconsistency. Current multi-core system is not adequate to increase memory-level parallelism and cache performance due to its poor core-to-core interconnection topology. In some architecture, like MIT Raw, each node/core has computing and switching components. Switching component of such a node consumes power while the node is only computing and vice versa. In this paper, we propose a design methodology to reduce the number of switches in multi-core architecture without compromising the performance. According to this method, nodes are separated between computing cores and network switches. Using folded torus topology, we develop a scheme to connect the components (cores and switches) in the multi-core architecture. We use multi-core architectures with various numbers of nodes (cores and switches) to evaluate the proposed methodology. Using synthetic workload, we obtain the core-to-core communication delay and total power consumption for MIT RAW, Triplet Based Architecture (TriBA), Logic-Based Distributed Routing (LBDR), and the proposed architecture. Experimental results show that the proposed architecture outperforms Raw, TriBA, and LBDR by cutting down the need for the number of switches significantly. According to the results, proposed architecture reduces total power consumption approximately by 77% and average delay by 54%. Power reduction comes from the fact that number of switches is cut down. Average delay is decreased as each switch provides adequate communicate channels.en_US
dc.format.extentxi, 55 p.en
dc.identifier.othert11091
dc.identifier.urihttp://hdl.handle.net/10057/5163
dc.language.isoen_USen_US
dc.publisherWichita State Universityen_US
dc.rightsCopyright Sri Ramya Chaturvedula, 2011. All rights reserveden
dc.subject.lcshElectronic dissertationsen
dc.titleDesigning multi-core architecture using folded torus concept to minimize the number of switchesen_US
dc.typeThesisen_US
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