Show simple item record

dc.contributor.authorAsaduzzaman, Abu
dc.contributor.authorSuryanarayana, Vidya R.
dc.contributor.authorSibai, Fadi N.
dc.identifier.citationAsaduzzaman, Abu; Suryanarayana, Vidya R.; Sibai, Fadi N. 2013. On level-1 cache locking for high-performance low-power real-time multicore systems. Computers & Electrical Engineering, Available online 16 April 2013en_US
dc.descriptionClick on the DOI link to access the article (may not be free).en_US
dc.description.abstractMultiple caches in multicore architecture increase power consumption and timing unpredictability. Although cache locking in single-core systems shows improvement for large multithreaded applications, there is no such effective strategy for multicore systems. In this work, we propose three level-1 cache locking strategies for multicore systems – static, random, and dynamic. In the random strategy, blocks are randomly selected for locking. The static and dynamic schemes are based on the analysis of applications’ worst case execution time (WCET). The static scheme does not allow unlocking blocks during runtime, but the dynamic scheme does. Using VisualSim and Heptane tools, we simulate a system with four cores and two levels of caches. According to the simulation results, the dynamic cache locking strategy outperforms the static and random strategies by up to 35% in mean delay per task and up to 22% in total power consumption for the workloads used (e.g., MPEG3 and MPEG4).en_US
dc.relation.ispartofseriesComputers & Electrical Engineering;Available online 16 April 2013
dc.titleOn level-1 cache locking for high-performance low-power real-time multicore systemsen_US
dc.description.versionPeer reviewed
dc.rights.holderCopyright © 2013, Elsevier

Files in this item


There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record