A directory based mechanism to minimize communication latency in multicore architectures by using wireless routers
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Multicore systems provide a high performance/power ratio by dividing the large jobs into smaller tasks and executing the tasks concurrently using multiple cores at a lower frequency. New software applications are written to generate more threads to take advantage of this multicore architecture. Contemporary multicore architectures have multilevel cache memory configurations and each core in a multicore system has its own private cache, Therefore multicore architectures suffer from high core-to-core communication latency due to the caches dynamic behavior. Studies suggest that a directory can be used to reduce communication latency by storing the information about the cache blocks. Recent studies also suggest that a wireless router has the potential to decrease communication latency in multicore architectures. In this work, we propose a directory based mechanism to minimize communication latency in a multicore architecture by using wireless routers. We model a 2D mesh, a newly introduced wireless NoC (WNoC), and our proposed directory-based architectures. According to the experimental results obtained using synthetic workloads, the proposed architecture outperforms the 2D mesh and WNoC. It is observed that the proposed architecture decreases the communication delay by up to 63% and the total power consumption by up to 33%. This is due to the fact that the proposed directory-based architecture helps reduce the total number of hops. This work can be extended to explore the impact of a directory on various concurrent/parallel techniques in multicore systems including data-level-parallelism and memory-level-parallelism.
Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and Computer Science