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dc.contributor.authorAsaduzzaman, Abu
dc.contributor.authorMahgoub, Imad O.
dc.contributor.authorYousif, Mazin S.
dc.date.accessioned2019-09-10T20:32:46Z
dc.date.available2019-09-10T20:32:46Z
dc.date.issued2000-04-03
dc.identifier.citationAsaduzzaman, A., Mahgoub, I., Yousif, M., "Memory latency evaluation in cluster-based cache coherent multiprocessor with different network topologies," in (CATA-98, pp. 393-396) International Symposium on Computer Architecture (ISCA), Honolulu, Hawaii, March 1998.
dc.identifier.issn0045-7906
dc.identifier.urihttp://dx.doi.org/10.1016/S0045-7906(99)00042-7
dc.identifier.urihttp://hdl.handle.net/10057/16582
dc.descriptionClick on the DOI link to access the article (may not be free).
dc.description.abstractThis research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. Each node in a cluster includes a small number of processors and a portion of the shared-memory, which are all connected through a split transaction bus. Each processor has two levels of caches. As the number of processors in a node is small, a snoopy cache coherence protocol is used. Inter-nodes cache coherence is maintained using a directory scheme. Nodes of the cluster are connected through an interconnection network: three networks have been chosen for this work, namely, ring, mesh and hypercube. Trace-driven simulation, driven by application traces from the Stanford SPLASH2 suite, has been developed to evaluate the overall memory latency of this architecture with the selected network topologies. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies.
dc.language.isoen_US
dc.publisherElsevier
dc.relation.ispartofseriesComputers and Electrical Engineering
dc.subjectBuffer storage
dc.subjectComputer architecture
dc.subjectComputer simulation
dc.subjectElectric network topology
dc.subjectInterconnection networks
dc.titleEvaluation of memory latency in cluster-based cache-coherent multiprocessor systems with different interconnection topologies
dc.typeArticle
dc.rights.holderCopyright Elsevier


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  • Articles [10]
    Selected research articles by Dr. Abu Asaduzzaman

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