Evaluation of memory latency in cluster-based cache-coherent multiprocessor systems with different interconnection topologies

Abstract

This research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. Each node in a cluster includes a small number of processors and a portion of the shared-memory, which are all connected through a split transaction bus. Each processor has two levels of caches. As the number of processors in a node is small, a snoopy cache coherence protocol is used. Inter-nodes cache coherence is maintained using a directory scheme. Nodes of the cluster are connected through an interconnection network: three networks have been chosen for this work, namely, ring, mesh and hypercube. Trace-driven simulation, driven by application traces from the Stanford SPLASH2 suite, has been developed to evaluate the overall memory latency of this architecture with the selected network topologies. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies.