A way cache locking scheme supported by knowledge based smart preload effective for low-power multicore electronics

Abstract

Adopting multicore architecture in consumer and bio-inspired electronics is promising to fulfill the growing need of high-performance. However, multi-level caches in multicore architecture require significant amount of power to be operated. In such a multi-level cache system, parallel thread execution becomes extremely difficult, which may also cause performance detraction. Studies suggest that cache locking has potential to decrease total power consumption and increase performance by reducing cache misses. In this work, a promising cache locking strategy for multicore electronics is proposed. According to this strategy, preselected blocks are preloaded knowingly at shared level cache and way cache locking is performed to lock all or some of those blocks. We model two multicore architectures: one Xeon-like quad-core system where CL2 is shared and one Opteron-like quad-core system where CL3 is shared. Popular MPEG-4, MPEG-3, JPEG, GIF, and FFT applications are used to run the simulation programs. Experimental results suggest that the proposed cache locking strategy is beneficial for designing low-power cache memory subsystem for multicore devices. Using proposed cache locking scheme, power consumption per task and mean delay per task are decreased by 41.12% and 35.51%, respectively, for MPEG-4 workload.