Directory-based wired-wireless network-on-chip architectures to improve performance
Chidella, Kishore K.
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Network-on-Chip (NoC) architectures have emerged as a promising technology for modern computer systems to address the design challenges of high-performance computing systems. Wireless NoC (WNoC) architectures are introduced to improve performance by reducing the core-to-core communication latency. Conventional WNoCs broadcast messages that increase bandwidth-traffic, communication latency, and power consumption. Studies show that directory-based schemes have potential to reduce bandwidth-traffic and improve performance. This work introduces a WNoC architecture with centralized directory (WNoC-CD) and a WNoC architecture with distributed directories (WNoC-DDs) to enhance faster execution by reducing bandwidth-traffic and communication latency. The impacts of uniform and non-uniform distribution of cores into subnets on performance are also studied. VisualSim software package is used to model and simulate a traditional mesh and the proposed WNoC-CD and WNoC-DDs architectures by processing different communication scenarios. Experimental results show that the proposed WNoC-DDs reduces communication latency up to 20.54% and 5.40%, respectively, when compared to mesh and WNoC-CD. Similarly, the proposed WNoC-DDs reduces power consumption up to 73.56% and 19.97%, respectively, when compared to mesh and WNoC-CD. In a WNoC-DDs, each subnet works independently and resolves communication issues simultaneously. Experimental results also show that the non-uniform subnets help reduce communication latency up to 11.11% and reduces power consumption up to 14.76% when compared with the uniform subnets. Non-uniform partitioning provides flexibility of allocating tasks to different sized subnets as needed and thus improves the core utilization to a greater extent.
Thesis (Ph.D.)-- Wichita State University, College of Engineering, Dept. of Electrical Engineering & Computer Science