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dc.contributor.authorAsaduzzaman, Abu
dc.contributor.authorChidella, Kishore K.
dc.date.accessioned2017-06-18T00:21:49Z
dc.date.available2017-06-18T00:21:49Z
dc.date.issued2016
dc.identifier.citationA. Asaduzzaman and K. K. Chidella, "A novel directory based hybrid cache coherence protocol for shared memory multiprocessors," 2016 IEEE International Symposium on Phased Array Systems and Technology (PAST), Waltham, MA, 2016, pp. 1-6en_US
dc.identifier.isbn978-1-5090-1447-7
dc.identifier.issn1554-8422
dc.identifier.otherWOS:000401796900053
dc.identifier.urihttp://dx.doi.org/10.1109/ARRAY.2016.7832588
dc.identifier.urihttp://hdl.handle.net/10057/13356
dc.descriptionClick on the DOI link to access the article (may not be free).en_US
dc.description.abstractWhile addressing cache coherency in shared memory multiprocessors, traditional snoopy based pure write update (PWU) and pure write invalidate (PWI) protocols have many issues including low bandwidth, high memory latency, and large cache miss ratio. This paper presents a directory based hybrid cache coherence protocol to better address the cache coherency and improve performance of shared memory multiprocessors. The requests to be processed are selected by using the proposed directory scheme and considering priority through non-starving mode to facilitate small sharer groups with a reasonable waiting time. Different read and write requests on 8-, 16-, and 32-core multiprocessors are considered. Experimental results show that the proposed strategy decreases bandwidth requirement about 37% than the PWU strategy. The results also indicate that the proposed strategy decreases memory latency by up to 12% and cache miss ratio by up to 22% when compared with those of the PWI strategy.en_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.ispartofseries2016 IEEE International Symposium on Phased Array Systems and Technology (PAST);
dc.subjectBandwidthen_US
dc.subjectCache coherence protocolen_US
dc.subjectCache miss ratioen_US
dc.subjectMemory latencyen_US
dc.subjectPure write invalidateen_US
dc.subjectPure write updateen_US
dc.subjectShared memory multiprocessorsen_US
dc.titleA novel directory based hybrid cache coherence protocol for shared memory multiprocessorsen_US
dc.typeConference paperen_US
dc.rights.holderCopyright © 2016, IEEEen_US


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