Implementation performance analysis comparison for two methods of implementing a fourth-order Chebyshev type II cascode NTF delta sigma converter architecture
There is increasing interest in continuous-time implementations of sigma-delta modulators, especially for high-speed and low-power applications. This is primarily due to some important advantages continuous-time realizations have compared to their switched-capacitor counterparts: can operate at higher sampling frequencies. Chebyshev cascode architecture is one of the promising architectures to implement in continuous-time domain. In this thesis, two circuit topologies are proposed to implement a fourth order Chebyshev type II cascode filter in continuous-time for use as a noise transfer function (NTF) in a delta-sigma data converter. These circuits were validated and performance analysis was done. The first circuit topology involves splitting a fourth order filter into two second order filters, and then cascoding them together. The over all filter was implemented using ideal components. Each second order filter was implemented using a biquad circuit with four op-amps. In the second circuit topology the fourth order filter was split into two second order filters and then cascoded similar to the first circuit topology. In this circuit topology, every second order filter was implemented using only one op-amp, as compared to four op-amps in the first circuit topology. The performance analysis of the circuit was done using SPICE. The obtained result was exported to workspace of Matlab, where the spectral analysis was obtained using Welch algorithm. This method shows that the proposed cascode architecture is robust and gives valuable information that is the best way to implement the circuit hardware.
Thesis (M.S.)-- Wichita State University, College of Engineering, Dept. of Electrical Engineering and Computer Science
- Master's Theses