Improving performance, power, and security of multicore systems using smart cache organization
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The need of multicore/manycore systems for today's world is significantly increasing. But the multicore system is considered to be power-hungry as well as high latency system. Different researches show that it is possible to increase the performance to power ratio by wisely locking the memory blocks inside the cache memory. But this method introduces cache underutilization problem which reduces the effective cache size and also it is hard to configure. Also depending on the processor type, some processor may not have the option of cache locking. Also cache side channel attack and cache interference become a security threat for the cache design. In this paper, a smart cache technique is proposed which decreases the memory access latency and cache power consumption, as well as increases the overall system security. Propose smart victim cache (SVC) between level-1 cache (CL1) and leve-2 cache (CL2) eliminates the cache locking. SVC holds the higher missing memory blocks and also supports stream buffering. For security improvement for the cache, we randomize the cache mapping between main memory and CL1. The randomized cache mapping makes the attacker fool by showing the false positions of the memory blocks in the cache. In the experiment, a quad-core Intel-type system is used, where CL1 is private and CL2 is shared among the cores. A tree based analyzer HEPTANE (Hades Embedded Processor Timing Analyzer) and a system level simulator VisualSim are used on diverse applications (including MPEG-4 and H.264/AVC). From the simulation results, it is seen that 17% of memory access latency and 21% of total power consumption is reduced using SVC comparing with cache locking without using SVC. For 16-block CL1, it is estimated that the probability of cache side channel attack reduces from 40K to 1.
Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and Computer Science