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dc.contributor.authorPendse, Ravi
dc.contributor.authorTambe, N.
dc.contributor.authorWalterscheidt, U.
dc.date.accessioned2011-09-29T15:46:50Z
dc.date.available2011-09-29T15:46:50Z
dc.date.issued1997-08-06
dc.identifier.citationPendse, R.; Tambe, N.; Walterscheidt, U.; , "A novel graphical technique for analysis of runtime cache behavior," Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on , vol.2, no., pp. 1322- 1325 vol.2, 3-6 Aug. 1997 doi: 10.1109/MWSCAS.1997.662325en_US
dc.identifier.isbn0780336941
dc.identifier.urihttp://hdl.handle.net/10057/3847
dc.identifier.urihttp://dx.doi.org/10.1109/MWSCAS.1997.662325
dc.descriptionThe full text of this article is not available on SOAR. WSU users can access the article via IEEE Xplore database licensed by University Libraries: http://libcat.wichita.edu/vwebv/holdingsInfo?bibId=1045954en_US
dc.description.abstractA novel technique is introduced to graphically analyze the runtime behavior of block replacement algorithms used in cache controllers. The new method allows a behavioral comparison of two or more algorithms, previously impossible due to the vast amount of data involved in cache simulations. Absolute and relative comparisons are demonstrated and the application in the development of a modified LRU is shown.en_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.ispartofseriesCircuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on;vol.2, no., pp. 1322- 1325
dc.subjectAlgorithm design and analysisen_US
dc.subjectAnalytical modelsen_US
dc.subjectApplication softwareen_US
dc.subjectCache memoryen_US
dc.subjectComputational modelingen_US
dc.subjectDegradationen_US
dc.subjectRelaysen_US
dc.subjectRuntimeen_US
dc.subjectThroughputen_US
dc.titleA novel graphical technique for analysis of runtime cache behavioren_US
dc.typeConference paperen_US
dc.description.versionPeer reviewed article
dc.rights.holder© IEEE, 1997


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