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dc.contributor.authorBhagavathula, Ravi
dc.contributor.authorChittoor, P.
dc.contributor.authorPendse, Ravi
dc.date.accessioned2011-09-20T15:45:46Z
dc.date.available2011-09-20T15:45:46Z
dc.date.issued2000
dc.identifier.citationBhagavathula, R.; Chittoor, P.; Pendse, R.; , "Pipeline LRU block replacement algorithm," Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, vol.1, no., pp.404-407 vol.1, 2000 doi: 10.1109/MWSCAS.2000.951669en_US
dc.identifier.isbn0780364759
dc.identifier.urihttp://hdl.handle.net/10057/3801
dc.identifier.urihttp://dx.doi.org/10.1109/MWSCAS.2000.951669
dc.descriptionThe full text of this article is not available on SOAR. WSU users can access the article via IEEE Xplore database licensed by University Libraries: http://libcat.wichita.edu/vwebv/holdingsInfo?bibId=1045954en_US
dc.description.abstractRecent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement schemeen_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.ispartofseriesCircuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on;vol.1, no., pp.404-407
dc.subjectAlgorithm design and analysisen_US
dc.subjectClocksen_US
dc.subjectMicroprocessorsen_US
dc.subjectPipelinesen_US
dc.subjectProcess designen_US
dc.subjectRandom access memoryen_US
dc.subjectTimingen_US
dc.subjectVery large scale integrationen_US
dc.subjectVLSIen_US
dc.subjectCache storageen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectPipeline processingen_US
dc.subjectSemiconductor storageen_US
dc.titlePipeline LRU block replacement algorithmen_US
dc.typeConference paperen_US
dc.description.versionPeer reviewed article
dc.rights.holder© IEEE, 2000


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