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Pipeline LRU block replacement algorithm

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dc.contributor.author Bhagavathula, Ravi
dc.contributor.author Chittoor, P.
dc.contributor.author Pendse, Ravi
dc.date.accessioned 2011-09-20T15:45:46Z
dc.date.available 2011-09-20T15:45:46Z
dc.date.issued 2000
dc.identifier.citation Bhagavathula, R.; Chittoor, P.; Pendse, R.; , "Pipeline LRU block replacement algorithm," Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, vol.1, no., pp.404-407 vol.1, 2000 doi: 10.1109/MWSCAS.2000.951669 en_US
dc.identifier.isbn 0780364759
dc.identifier.uri http://hdl.handle.net/10057/3801
dc.identifier.uri http://dx.doi.org/10.1109/MWSCAS.2000.951669
dc.description The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xplore database licensed by University Libraries: http://libcat.wichita.edu/vwebv/holdingsInfo?bibId=1045954 en_US
dc.description.abstract Recent advances in VLSI technology have spurred a tremendous increase in the performance of processors. Due to the slower main memory, there exists a bottleneck in the performance of computer systems. Caching is an effective way to reduce these bottlenecks. With increasing cache sizes, the performance of the processor could be enhanced by using advanced block replacement algorithms like LRU etc. However, due to the presence of the cache in the critical timing path, many processors do not employ these advanced replacement policies. In this paper, the authors present an alternative implementation of block replacement algorithms in CPU caches by modifying the processor pipeline to hide the latency involved in the replacement scheme en_US
dc.language.iso en_US en_US
dc.publisher IEEE en_US
dc.relation.ispartofseries Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on;vol.1, no., pp.404-407
dc.subject Algorithm design and analysis en_US
dc.subject Clocks en_US
dc.subject Microprocessors en_US
dc.subject Pipelines en_US
dc.subject Process design en_US
dc.subject Random access memory en_US
dc.subject Timing en_US
dc.subject Very large scale integration en_US
dc.subject VLSI en_US
dc.subject Cache storage en_US
dc.subject Microprocessor chips en_US
dc.subject Pipeline processing en_US
dc.subject Semiconductor storage en_US
dc.title Pipeline LRU block replacement algorithm en_US
dc.type Conference paper en_US
dc.description.version Peer reviewed article
dc.rights.holder © IEEE, 2000

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